When a semiconductor device, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), is scaled down through various technology nodes, high dielectric constant (high-k) gate dielectric layer and metal gate electrode layer are incorporated into the gate stack of the MOSFET to improve device performance with the decreased feature sizes. In addition, strained structures in source and drain (S/D) recess cavities of the MOSFET utilizing selectively grown silicon germanium (SiGe) may be used to enhance carrier mobility. The selective growth processes, however, suffer from drawbacks.
FIG. 1 shows a cross-sectional view of a semiconductor device 100 with conventional strained structures 120 in the source and drain (S/D) recess cavities. The semiconductor device 100 can be formed over an active region 106 of a substrate 102 adjacent to isolation regions 104. The semiconductor device 100 comprises lightly doped source/drain (LDD) regions 118 and source/drain (S/D) regions 120 formed in the active region 106 of the substrate 102, silicide regions 130 formed over the S/D regions 120, a gate stack 110 comprising a gate dielectric layer 114 and a gate electrode layer 112 sequentially formed over the substrate 102, and a pair of spacers 116 formed at two sides of the gate stack 110.
However, there are challenges to implement such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication. As the gate length and spacing between devices decrease, these problems are exacerbated. For example, problems arise in the selective growth processes that form the strained structures 120 in the S/D recess cavities. Since heterogeneous nucleation reactions during the selective growth processes may occur, particles 120a may be formed on the surfaces of the gate stack 110, gate spacers 116 and isolation regions 104. If they are not fully removed by subsequent clean processes, the un-removed particles 120a may become embedded in the semiconductor device 100. The un-removed particles 120a may provide carrier transportation paths during device operation, thereby increasing the likelihood of device instability and/or device failure.
Accordingly, what is needed is a method for fabricating a strained structure having no particle in a semiconductor device.